Packaging defects mainly include lead deformation, base offset, warpage, chip breakage, delamination, voids, uneven packaging, burrs, foreign particles and incomplete curing, etc.
1. Lead deformation
Lead deformation usually refers to the lead displacement or deformation caused during the flow of plastic sealant, which is usually expressed by the ratio x/L between the maximum lateral lead displacement x and the lead length L. Lead bending can lead to electrical shorts (especially in high density I/O device packages). Sometimes the stresses generated by bending can lead to cracking of the bonding point or a reduction in bond strength.
Factors that affect lead bonding include package design, lead layout, lead material and size, molding plastic properties, lead bonding process, and packaging process. Lead parameters that affect lead bending include lead diameter, lead length, lead break load and lead density, etc.
2. Base offset
Base offset refers to the deformation and offset of the carrier (chip base) that supports the chip.
Factors that affect base shift include the flow of the molding compound, the leadframe assembly design, and the material properties of the molding compound and leadframe. Packages such as TSOP and TQFP are susceptible to base shift and pin deformation due to their thin leadframes.
3. Warpage
Warpage is the out-of-plane bending and deformation of the package device. Warpage caused by the molding process can lead to a number of reliability issues such as delamination and chip cracking.
Warpage can also lead to a range of manufacturing problems, such as in plasticized ball grid array (PBGA) devices, where warpage can lead to poor solder ball coplanarity, causing placement problems during reflow of the device for assembly to a printed circuit board.
Warpage patterns include three types of patterns: inward concave, outward convex and combined. In semiconductor companies, concave is sometimes referred to as “smiley face” and convex as “cry face”. The main causes of warpage include CTE mismatch and cure/compression shrinkage. The latter did not receive much attention at first, but in-depth research revealed that chemical shrinkage of the molding compound also plays an important role in IC device warpage, especially in packages with different thicknesses on the top and bottom of the chip.
During the curing and post-curing process, the molding compound will undergo chemical shrinkage at high curing temperature, which is called “thermochemical shrinkage”. The chemical shrinkage that occurs during curing can be reduced by increasing the glass transition temperature and reducing the change in coefficient of thermal expansion around Tg.
Warpage can also be caused by factors such as the composition of the molding compound, moisture in the molding compound, and the geometry of the package. By controlling the molding material and composition, process parameters, package structure and pre-encapsulation environment, package warpage can be minimized. In some cases, warpage can be compensated by encapsulating the back side of the electronic assembly. For example, if the external connections of a large ceramic board or multilayer board are on the same side, encapsulating them on the back side can reduce warpage.
4. Chip breakage
The stresses generated in the packaging process can lead to chip breakage. The packaging process usually aggravates the micro-cracks formed in the previous assembly process. Wafer or chip thinning, backside grinding, and chip bonding are all steps that can lead to the sprouting of cracks.
A cracked, mechanically failed chip does not necessarily lead to electrical failure. Whether a chip rupture will result in instantaneous electrical failure of the device also depends on the crack growth path. For example, if the crack appears on the back side of the chip, it may not affect any sensitive structures.
Because silicon wafers are thin and brittle, wafer-level packaging is more susceptible to chip rupture. Therefore, process parameters such as clamping pressure and molding transition pressure in the transfer molding process must be strictly controlled to prevent chip rupture. 3D stacked packages are prone to chip rupture due to the stacking process. The design factors affecting chip rupture in 3D packages include chip stack structure, substrate thickness, molding volume and mold sleeve thickness, etc.
Post time: Feb-15-2023